1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and, more particularly, to an electrically erasable non-volatile semiconductor memory device (EEPROM).
2. Description of the Background Art
FIG. 5 is a circuit diagram illustrating a main part of a conventional non-volatile semiconductor memory device. Referring to FIG. 5, a plurality of memory transistors 1-4 are arranged in a matrix manner in the row direction and the column direction. Although only four memory transistors are illustrated in FIG. 5 for simplification, a larger number of memory transistors are arranged in practice. The control gates of memory transistors 1, 2 arranged in the same row are connected in common to a word line 5, and the control gates of memory transistors 3, 4 arranged in the same row are connected in common to a word line 6. The drains of memory transistors 1, 3 arranged in the same column are connected in common to a bit line 7, and the drains of memory transistors 2, 4 arranged in the same column are connected in common to a bit line 8. The sources of memory transistors 1-4 are connected in common to a source line 9. Source line 9 is connected to a high voltage/ground voltage switching circuit 10. A transistor 11 has the gate connected to a Y gate line 13 and the source connected to bit line 7. A transistor 12 has the gate connected to a Y gate line 14 and the source connected to bit line 8. The drain of each of transistors 11, 12 is connected to a write driver 15 as well as to a sense amplifier 16.
Word lines 5, 6 are connected to an X decoder 17. A decoding circuit in X decoder 17 includes an NAND gate 18 and transistors 19-22. NAND gate 18 has the input connected to an X address buffer 23 and the output connected to the source of transistor 19. A supply voltage Vcc is applied to the gate of transistor 19. Accordingly, transistor 19 is always in ON state. The drain of transistor 19 is connected to the drain of transistor 20 and to the gates of transistors 21, 22. A high voltage Vh and the supply voltage Vcc (Vh&gt;Vcc) from a high voltage/supply voltage switching circuit (not shown) are selectively applied through terminals 37 to the sources of transistors 20, 21. The source of transistor 22 is grounded. The drains of transistors 21, 22 are connected in common to the gate of transistor 20 and to word line 5. A decoding circuit having the same structure as the above-described one is provided for each word line in X decoder 17. A buffer circuit in X address buffer 23 includes inverters 24-26 and provides outputs Xi and Xi for an address input Xi. Output Xi is an inversion signal of output Xi. X address buffer 23 includes the same number of buffer circuits of the above-described structure as the number of the bits of an X address. NAND gate 18 in each of the above decoding circuits selectively receives either the output of inverter 25 or the output of inverter 26 from corresponding one of the above buffer circuits.
Y gate lines 13, 14 are connected to a Y decoder 27. A decoding circuit in Y decoder 27 includes an NAND gate 28 and transistors 29-32. NAND gate 28 has the input connected to a Y address buffer 33 and the output connected to the source of transistor 29. Supply voltage Vcc is applied to the gate of transistor 29. Accordingly, transistor 29 is always in ON state. The drain of transistor 29 is connected to the drain of transistor 30 and to the gates of transistors 31, 32. High voltage Vh and supply voltage Vcc from the high voltage/supply voltage switching circuit (not shown) are selectively applied through a terminal 37 to the sources of transistors 30, 31. The source of transistor 32 is grounded. The drains of transistors 31, 32 are connected to the gate of transistor 30 and to Y gate line 13. Y decoder 27 includes decoding circuits each having the same structure as the above-described one for respective Y gate lines. A buffer circuit in a Y address buffer 33 includes inverters 34-36 and provides outputs Yi and Yi for an address input Yi. Output Yi is an inversion signal of output Yi. Y address buffer 33 includes the same number of buffer circuits each having the above-described structure as the number of the bits of a Y address. NAND gate 28 in each of the above decoding circuits selectively receives either the output of inverter 35 or the output of inverter 36 from corresponding one of the above buffer circuits.
FIG. 6 is a sectional view illustrating a sectional structure of any one of memory transistors 1-4 illustrated in FIG. 5. Referring to FIG. 6, a diffused drain region 52 and a diffused source region 53 are formed spaced a predetermined distance apart from each other on a part of a P-type semiconductor substrate 51. An extremely thin tunnel oxide film 54 is formed on P-type semiconductor substrate 51, and a floating gate 55 is formed thereon. An oxide film 56 is formed on floating gate 55, and a control gate 57 is formed thereon. Writing into the memory transistor illustrated in FIG. 6 is carried out by applying a high voltage to diffused drain region 52 and to control gate 57 and grounding diffused source region 53. Consequently, an avalanche breakdown occurs in the vicinity of diffused drain region 52, and hot electrons caused by it are injected through tunnel oxide film 54 into floating gate 55. Then, the threshold value of the memory transistor becomes high.
Erasing of the memory transistor illustrated in FIG. 6 is carried out by bringing diffused drain region 52 to a floating state, applying a high voltage to diffused source region 53, and grounding control gate 57. Consequently, electrons are extracted from floating gate 55 through tunnel oxide film 54 to diffused source region 53 by a tunnel phenomenon. Then, the threshold voltage of the memory transistor becomes low.
Now, operation of the conventional non-volatile semiconductor memory device illustrated in FIG. 5 will be described.
First, the erase operation will be described. Erasing is carried out collectively in the whole chip. Y decoder 27 makes the potentials of both of Y gate lines 13, 14 to attain a low or "L" level. This causes transistors 11, 12 to be in OFF state. X decoder 17 makes the potentials of both of word lines 5, 6 to attain "L" level. A high voltage is applied to source line 9 by high voltage/ground voltage switching circuit 10. This causes electrons extracted from the floating gates of memory transistors 1-4 and the threshold values of memory transistors 1-4 to be low. The erasing time at this time is externally controlled.
Now, the write operation will be described. The case where writing into memory transistor 1 is carried out will be described as an example. A high voltage is applied to the drains of transistors 11, 12 by write driver 15. A high voltage is applied from the high voltage/supply voltage switching circuit not shown through terminal 37 to the source of each of transistors 20, 21, 30 and 31. Y decoder 27 applies a high voltage to a selected Y gate line 13 and makes the potential of the non-selected other Y gate line 14 attain "L" level. Therefore, transistor 11 is turned on, and transistor 12 is turned off. X decoder 17 applies a high voltage to a selected word line 5 and makes the potential of the non-selected other word line 6 attain "L" level. Source line 9 is grounded by high voltage/ground voltage switching circuit 10. This causes an avalanche breakdown to occur in the vicinity of the drain of memory transistor 1, and generated hot electrons are injected into the floating gate. Therefore, the threshold value of memory transistor 1 becomes high. The writing time at this time is externally controlled.
Now, the read operation will be described. The case where reading from memory transistor 1 is carried out will be described as an example. The supply voltage is applied from the high voltage/supply voltage switching circuit not shown through terminal 37 to the source of each of transistors 20, 21, 30, and 31. Y decoder 27 makes the potential of a selected Y gate line 13 attain "H" level and makes the potential of the non-selected other Y gate line 14 attain "L" level. Therefore, transistor 11 is turned on, and transistor 12 is turned off. X decoder 17 makes the potential of a selected word line 5 attain "H" level and makes the potential of the non-selected other word line 6 attain "L" level. Source line 9 is grounded by high voltage/ground voltage switching circuit 10. If memory transistor 1 is in the writing state (a state in which the threshold value is high), memory transistor 1 remains off, and no current flows in bit line 7. On the other hand, if memory transistor 1 is in the erasing state (a state in which the threshold value is low), memory transistor 1 is turned on, and current flows in bit line 7. Reading is carried out by sensing the presence and absence of the current by sense amplifier 16.
The conventional non-volatile semiconductor memory device is constituted as described above, so that if the erasing time is erroneously lengthened, more electrons than necessary are extracted from the floating gate of a memory transistor, and the memory transistor is brought to a depletion (over-erase) state. If the memory transistor is brought to the over-erase state, the memory transistor is always in ON state, and subsequent reading/erasing/reading cannot be normally carried out.